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ap7175 document number: ds35606 rev. 3 - 2 1 of 14 www.diodes.com december 2012 ? diodes incorporated new product a p7175 3a ultra low dropout linear regulator with enable description the ap7175 is a 3.0a ultra low-dropout (ldo) linear regulator that features an enable input and a power-good output. the enable input and power-good output allow users to configure power management solutions that can meet the sequencing requirements of fpgas, dsps, and ot her applications with different start-up and power-down requirements. the ap7175 features two supply input s, for power conversion supply and control. with the separation of the control and the power input very low dropout voltages can be reached and power dissipation is reduced. a precision reference and feedback control deliver 1.5% accuracy over load, line, and operating temperature ranges. the ap7175 is available in so-8ep and msop-8ep package with an exposed pad to reduce the junction to case resistance and extend the temperature range it can be used in. features ? v in range: 1.2v to 3.65v v cntl 3.0v to 5.5v ? adjustable output voltage ? continuous output current i out = 3a ? fast transient response ? power on reset monitoring on v cntl and v in ? internal softstart ? stable with low esr mlcc capacitors ? totally lead-free & fully rohs compliant (notes 1 & 2) ? halogen and antimony free. ?green? device (note 3) pin assignments applications ? notebook ? pc ? netbook ? wireless communication ? server ? motherboard ? dongle ? front side bus vtt (1.2v/3.3a) notes: 1. no purposely added lead. fully eu directiv e 2002/95/ec (rohs) & 2011/6 5/eu (rohs 2) compliant. 2. see http://www.diodes.com for more in formation about diodes incorpor ated?s definitions of halogen- and antimony-free, "gree n" and lead-free. 3. halogen- and antimony-free "green? products are defined as those which contain <900ppm br omine, <900ppm chlorine (<1500ppm t otal br + cl) and <1000ppm antimony compounds. typical applications circuit on off pg vcntl vin en vout fb gnd c1 r1 r2 c in c out c cntl r3 * optional 10uf 1uf 5.1k ? 10uf 24k ? 12k ? ap7175 figure 1. typical application circuit
ap7175 document number: ds35606 rev. 3 - 2 2 of 14 www.diodes.com december 2012 ? diodes incorporated new product a p7175 pin descriptions pin name pin number function so-8ep msop-8ep gnd 1 1 ground fb 2 2 feedback to set the output voltage via an external resistor divider between v out and gnd. v out 3/4 3/4 power output pin. connect at least 10f capacitor to this pin to impr ove transient response and required for stability. when the part is disabled the output is discharged via an internal pull-low mosfet. v in 5 5 power input pin for current supply. connect a decoupling capacitor ( 10f) as close as possible to the pin for noise filtering. v cntl 6 6 bias supply for the controller, recomm ended 5v. connect a decoupling capacitor ( 1f) as close as possible to the pin for noise filtering. pg 7 7 power good output open drain to indicate the status of v out via monitoring the fb pin. this pin is pulled low when the voltage is outside the limits, during thermal shutdown and if either v cntl or v in go below their thresholds. en 8 8 enable pin. driving this pin low will disable the part. when left floating an internal current source will pull this pin high and enable it. pad ep ep exposed pad connect this to v in for good thermal conductivity. functional block diagram
ap7175 document number: ds35606 rev. 3 - 2 3 of 14 www.diodes.com december 2012 ? diodes incorporated new product a p7175 absolute maximum ratings (note 4) (@t a = +25c, unless otherwise specified.) symbol parameter rating unit v in v in supply voltage (v in to gnd) -0.3 to +4.0 v v cntl v cntl supply voltage (v cntl to gnd) -0.3 to +7.0 v v out v out to gnd voltage -0.3 to v in +0.3 v pg to gnd voltage -0.3 to +7.0 v en, fb to gnd voltage -0.3 to v cntl +0.3 v p d power dissipation (so-8ep) 1.7 w power dissipation (msop-8ep) 1.5 t j maximum junction temperature 150 c t stg storage temperature -65 to +150 c t sdr maximum lead soldering temperature, 10 seconds 260 c note: 4. stresses greater than the 'absolute maximum ratings' sp ecified above, may cause permane nt damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions exceeding those indicated in this specification is not implied. device reliability may be affected by exposure to absolute maximum rating conditions for extended periods of time. recommended operating conditions (@t a = +25c, unless otherwise specified.) symbol parameter min max unit v cntl v cntl supply voltage 3.0 5.5 v v in v in supply voltage 1.2 3.65 v v out v out output voltage (when v cntl -v out >1.9v) 0.8 v in - v drop v i out v out output current continuous current 0 3 a peak current 0 4 c out v out output capacitance i out = 3a at 25% nominal v out 8 1100 f i out = 2a at 25% nominal v out 8 1700 i out = 1a at 25% nominal v out 8 2400 e srcout esr of v out output capacitor 0 200 m ? t a ambient temperature -40 +85 c t j junction temperature -40 +125 c
ap7175 document number: ds35606 rev. 3 - 2 4 of 14 www.diodes.com december 2012 ? diodes incorporated new product a p7175 electrical characteristics (v cntl = 5v, v in = 1.8v, v out = 1.2v and t a = -40 to +85c, @t a = +25c, unless otherwise specified.) symbol parameter test conditions ap7175 unit min typ max supply current iv cntl v cntl supply current en = v cntl , i out =0a ? 1.0 1.5 ma i sd v cntl supply current at shutdown en = gnd ? 15 30 a v in supply current at shutdown en = gnd, v in =3.65v ? ? 1 a power-on-reset (por) rising v cntl por threshold 2.5 2.7 2.95 v v cntl por hysteresis ? 0.4 ? v rising v in por threshold 0.8 0.9 1.0 v v in por hysteresis ? 0.5 ? v output voltage v ref reference voltage fb = v out ? 0.8 ? v output voltage accuracy v cntl =3.0 ~ 5.5v, i out = 0 to 3a, t j = -40 to +125c -1.5 ? +1.5 % load regulation i out =0a to 3a ? 0.06 0.25 % line regulation i out =10ma, v cntl = 3.0 to 5.5v -0.15 ? +0.15 %/v v out pull-low resistance v cntl = 3.3v, v en = 0v, v out < 0.8v ? 10 ? ? fb input current v fb = 0.8v -100 ? 100 na dropout voltage v drop v in -to-v out dropout voltage (note 5) v cntl = 5.0v, i out = 3a v out = 2.5v t j = +25c 0.26 0.31 v t j = -40 to +125c 0.42 v out = 1.8v t j = +25c 0.24 0.29 t j = -40 to +125c 0.40 v out = 1.2v t j = +25c 0.23 0.28 t j = -40 to +125c 0.38 i lim current-limit level t j = +25c, v out = 80% v nominal 4.5 5.7 6.7 a t j = -40 to +125c 4.2 a protections i short short current-limit level v fb < 0.2v ? 1.1 ? a t sd thermal shutdown temperature t j rising ? 170 c thermal shutdown hysteresis ? 50 ? c enable and soft-start en logic high threshold voltage v en rising 0.5 0.8 1.1 v en hysteresis 0.1 ? v en pull-high current en = gnd ? 5 ? ua t ss soft-start interval 0.3 0.6 1.2 ms turn on delay from being enabled to v out rising 10% 200 350 500 us power-good and delay v thpg rising pg threshold voltage v fb rising 90 92 95 % pg threshold hysteresis ? 8 ? % pg pull-low voltage pg sinks 5ma ? 0.25 0.4 v pg debounce interval v fb < falling pg voltage threshold ? 10 ? s pg delay time from v fb = v thpg to rising edge of the v pg 1 2 4 ms note: 5. dropout voltage is the voltage diff erence between the inut and the output at which the output voltage drops 2% below its nominal value.
ap7175 document number: ds35606 rev. 3 - 2 5 of 14 www.diodes.com december 2012 ? diodes incorporated new product a p7175 electrical characteristics (cont.) (v cntl = 5v, v in = 1.8v, v out = 1.2v and t a = -40 to +85c, @t a = +25c, unless otherwise specified.) symbol parameter test conditions ap7175 unit min typ max thermal characteristic ja thermal resistance junction-to-ambient so-8ep (note 6) 70 c/w msop-8ep (note 7) 80 c/w jc thermal resistance junction-to-ambient so-8ep (note 6) 30 c/w msop-8ep (note 7) 30 c/w notes: 6. device mounted on 2"*2" fr-4 substrate pc board, 2oz copper, wi th minimum recommended pad on top layer and thermal vias to bott om layer ground plane. 7. device mounted on 2"*2" fr-4 substrate pc board, 2oz copper,wit h minimum recommended pad layout. typical characteristics
ap7175 document number: ds35606 rev. 3 - 2 6 of 14 www.diodes.com december 2012 ? diodes incorporated new product a p7175 typical characteristics (cont.)
ap7175 document number: ds35606 rev. 3 - 2 7 of 14 www.diodes.com december 2012 ? diodes incorporated new product a p7175 p o w e r o n c out =10f, c in =10f, r l =0.4 ? ch1: v cntl , 5v/div, dc ch2: v in , 1v/div, dc ch3: v out , 1v/div, dc ch4: v pok , 5v/div, dc time: 2ms/di v v in v c ntl v ou t v p o k p o w e r o ff c out =10f, c in =10f, r l =0.4 ? ch1: v cntl , 5v/div, dc ch2: v in , 1v/div, dc ch3: v out , 1v/div, dc ch4: v pok , 5v/div, dc time: 2ms/di v v in v c ntl v ou t v p o k load transient res p onse i out = 10ma to 3a to10ma (rise / fall time =1s) c out = 10f, c in = 10f ch1: v out , 50mv/div, ac ch2: i out , 1a/div, dc time: 50s/div v ou t i ou t over current protection c out = 10f, c in = 10f, i out = 2a to 5.6a ch1: v out , 0.5v/div, dc ch2: i out , 2a/div, dc time: 0.2ms/div v ou t i ou t operating waveforms (@ v cntl = 5v, v in = 1.8v, v out = 1.2v, t a = +25c, unless otherwise specified.)
ap7175 document number: ds35606 rev. 3 - 2 8 of 14 www.diodes.com december 2012 ? diodes incorporated new product a p7175 shutdown c out = 10f, c in = 10f, r l = 0.4 ? ch1: v en , 5v/div, dc ch2: v out , 1v/div, dc ch3: v pok , 5v/div, dc ch4: i out , 2a/div, dc time: 4 s/di v v en v out v p o k i out en ab l e c out = 10f, c in = 10f, r l = 0.4 ? ch1: v en , 5v/div, dc ch2: v out , 1v/div, dc ch3: v pok , 5v/div, dc ch4: i out , 2a/div, dc time: 1ms/di v v en v out v p o k i out operating waveforms (cont.) (@ v cntl = 5v, v in = 1.8v, v out = 1.2v, t a = +25c, unless otherwise specified.)
ap7175 document number: ds35606 rev. 3 - 2 9 of 14 www.diodes.com december 2012 ? diodes incorporated new product a p7175 application information power good and delay ap7175 monitors the feedback voltage v fb on the fb pin. an internal delay timer is started after the pg voltage threshold (v thpg ) on the fb pin is reached. at the end of the delay time an internal nmos of the pg is turned off to indicate that the power at the output is g ood (pg). this monitoring function is cont inued during operation and if v fb falls 8% (typ) below v thpg , the nmos of the pg is turned on after a delay time of typical 10s to avoid oscillating of the pg signal. power on reset ap7175 monitors both supply voltages, v cntl and v in to ensure operation as intended. a soft-start process is initiated after both voltages exceed their por threshold during power on. during operation the por component continues to monitor the supply voltage and pull s the pg low to indicate an out of regulation supply. this functi on will engage without regard to the status of the output. soft-start ap7175 incorporates an internal soft-start function. the output vo ltage rise is controlled to limit the current surge during st art-up. the typical soft-start time is 0.6ms. current-limit protection ap7175 monitors the current flow through the nmos and limits the maximum current to avoid damage to the load and ap7175 during overload conditions. short circuit current-limit protection ap7175 incorporates a current limit function to reduce the maximum current to 1.1a (typ) when the voltage at fb falls below 0.2 v (typ) during an overload or short ci rcuit situation. during start-up period, this function is dis abled to ensure successful heavy load start-up. enable control if the enable pin (en) is left open, an internal current source of ~5a pulls the pin up and enables the ap7175. this will redu ce the bill of material saving an external pull up resistor. driving the enable pin low di sables the device. driving t he pin high subsequently initiate s a new soft-start cycle. output voltage regulation output voltage is set by resistor divider from v out via fb pin to gnd. internally v fb is compared to a 0.8v temperature compensated reference voltage and the nmos pass element regulates the output voltage while delivering current from v in to v out . setting the output voltage a resistor divider connected to fb pin programs the output voltage. v 2r 1r 1* vv ref out ? ? ? ? ? ? + = r1 is connected from v out to fb with kelvin sensing connection. r2 is connected from fb to gnd. to improve load transient response and stability, a bypass capacitor can be connected in parallel with r1. (optional in ty pical application circuit) power sequencing ap7175 requires no specific sequencing between v in and v cntl . however, care should be taken to avoid forcing v out for prolonged times without the presence of v in . conduction through internal parasitic diode (from v out to v in ) could damage ap7175. thermal shutdown the pcb layout and power requirements for ap7175 under normal oper ation condition should allow enough cooling to restrict the j unction temperature to +125c. the packages for ap7175 have an exposed pad to support this. these pack ages provide better connection to the pcb and thermal performance. refer to the layout considerations. if ap7175 junction temperature reaches +170c a thermal protection block disables the nm os pass element and lets the part cool down. after its junction temperature drops by 50c (typ), a new soft-start cycle will be initiated. a new thermal protection will start, if the load or ambient conditions continue to raise the junction te mperature to +170c. this cycle will repeat until normal operation temperature is m aintained again.
ap7175 document number: ds35606 rev. 3 - 2 10 of 14 www.diodes.com december 2012 ? diodes incorporated new product a p7175 application information (cont.) output capacitor an output capacitor (c out ) is needed to improve transient response and maintain stability. the esr (equivalent series resistance) and capacitance drives the selection. care needs to be taken to cover the entire operating temperature range. the output capacitor can be an ultra-low-esr ceramic chip capacit or or a low esr bulk capacitor like a solid tantalum, poscap o r aluminum electrolytic capacitor. c out is used to improve the output stability and reduces the changes of the output voltage during load transitions. the slew rate o f the current sensed via the fb pin in ap7175 is reduced. if the application has large load variatio ns, it is recommended to utilize low-esr bulk capacitors. it is recommended to place ceramic capacitors as close as possible to the load and t he ground pin and care should be taken to r educe the impedance in the layout. input capacitor to prevent the input voltage from dropping during load st eps it is recommended to utilize an input capacitor (c in ). as with the output capacitor the following are acceptable, ultra-low-esr ceramic chip capacitor or low esr bulk capacitor like a solid tantalum, poscap or a luminum electrolytic capacitor. typically it is recommended to utilize an capacitance of at least 10f to avoid output voltage drop due to reduced input voltage. the value can be lower if v in changes are not critical for the application. layout considerations for good ground loop and stability, the input and output capacitors should be located close to the input, output, and ground pi ns of the device. no other application circuit is connected wi thin the loop. avoid using vias within ground loop. if vias must be used, multiple vias should be used to reduce via inductance. the regulator ground pin should be connected to the external circuit ground to reduce voltage drop caused by trace impedance. g round plane is generally used to reduce trace impedance. wide trace should be used for large current paths from v in to v out , and load circuit. place the r1, r2, and c1(optional) near the ldo as close as possible to avoid noise coupling. r2 is placed close to device ground. connect the ground of the r2 to the gnd pin by using a dedicated trace. connect the pin of the r1 directly to the load for kelvin sensing. no high current should flow through the ground trace of feedback loop and affect reference voltage stability. for the packages with exposed pads, heat sinking is accomplis hed using the heat spreading capability of the pcb and its copper traces. suitable pcb area on the top layer and thermal vias(0.3mm drill size with 1mm spaci ng, 4~8 vias at least) to the vin power plan e can help to reduce device temperature greatly. reference layout plots top layer bottom layer vin gnd en pg vin vout en cin cout gnd fb r1 r2 vcntl pg gnd 1 c1 ccntl
ap7175 document number: ds35606 rev. 3 - 2 11 of 14 www.diodes.com december 2012 ? diodes incorporated new product a p7175 ordering information part number package code packaging 13? tape and reel quantity part number suffix ap7175sp-13 sp so-8ep 2500/tape & reel -13 AP7175MP-13 mp msop-8ep 2500/tape & reel -13 marking information (1) so-8ep (2) msop-8ep
ap7175 document number: ds35606 rev. 3 - 2 12 of 14 www.diodes.com december 2012 ? diodes incorporated new product a p7175 package outline dimensions (all dimensions in mm.) please see ap02002 at http://www.diodes.com /datasheets/ap02002.pdf for latest version. (1) so-8ep (2) msop-8ep so-8ep (sop-8l-ep) dim min max typ a 1.40 1.50 1.45 a1 0.00 0.13 - b 0.30 0.50 0.40 c 0.15 0.25 0.20 d 4.85 4.95 4.90 e 3.80 3.90 3.85 e0 3.85 3.95 3.90 e1 5.90 6.10 6.00 e - - 1.27 f 2.75 3.35 3.05 h 2.11 2.71 2.41 l 0.62 0.82 0.72 n - - 0.35 q 0.60 0.70 0.65 all dimensions in mm msop-8ep dim min max typ a - 1.10 - a1 0.05 0.15 0.10 a2 0.75 0.95 0.86 a3 0.29 0.49 0.39 b 0.22 0.38 0.30 c 0.08 0.23 0.15 d 2.90 3.10 3.00 d1 1.60 2.00 1.80 e 4.70 5.10 4.90 e1 2.90 3.10 3.00 e2 1.30 1.70 1.50 e3 2.85 3.05 2.95 e - - 0.65 l 0.40 0.80 0.60 a 0 8 4 x - - 0.750 y - - 0.750 all dimensions in mm gauge plane seating plane e1 e n e b a 45 e0 h f exposed pad bottom view l q c 7 4 3 9 (all sides) a1 d 14 85 1 d a a1 a2 e e y x seating plane gauge plane l d 8xb see detail c detail c c a e1 e3 a3 e2 4 x 1 0 4 x 1 0 0.25 d1
ap7175 document number: ds35606 rev. 3 - 2 13 of 14 www.diodes.com december 2012 ? diodes incorporated new product a p7175 suggested pad layout please see ap02001 at http://www.diodes.com/dat asheets/ap02001.pdf for the latest version. (1) so-8ep (2) msop-8ep dimensions value (in mm) c 1.270 x 0.802 x1 3.502 x2 4.612 y 1.505 y1 2.613 y2 6.500 dimensions value (in mm) c 0.650 g 0.450 x 0.450 x1 2.000 y 1.350 y1 1.700 y2 5.300 g x c y y2 y1 x1 c y1 x1 x y y2 x2
ap7175 document number: ds35606 rev. 3 - 2 14 of 14 www.diodes.com december 2012 ? diodes incorporated new product a p7175 important notice diodes incorporated makes no warranty of any kind, express or implied, with regards to this document, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose (and their equivalents under the laws of any jurisdiction). diodes incorporated and its subsidiaries rese rve the right to make modifications, enhancements, improvements, corrections or ot her changes without further notice to this document and any product descri bed herein. diodes incorporated does not assume any liability arising out of the application or use of this document or any product described he rein; neither does diodes incorporated convey any license under its patent or trademark rights, nor the rights of others. any customer or user of this document or products described herein in such applica tions shall assume all risks of such use and will agree to hold diodes incorporated a nd all the companies whose products are represented on diodes incorporated website, harmless against all damages. diodes incorporated does not warrant or accept any liability whatsoever in respect of any products purchased through unauthoriz ed sales channel. should customers purchase or use diodes inco rporated products for any unintended or una uthorized application, customers shall i ndemnify and hold diodes incorporated and its representativ es harmless against all claims, damages, expenses, and attorney fees arising out of, directly or indirectly, any claim of personal injury or death a ssociated with such unintended or unauthorized application. products described herein may be covered by one or more united states, international or foreign patents pending. product names and markings noted herein may also be covered by one or more united states, international or foreign trademarks. this document is written in english but may be translated into multiple languages for reference. only the english version of t his document is the final and determinative format released by diodes incorporated. life support diodes incorporated products are specifically not authorized for use as critical com ponents in life support devices or systems without the express written approval of the chief executive offi cer of diodes incorporated. as used herein: a. life support devices or syst ems are devices or systems which: 1. are intended to implant into the body, or 2. support or sustain life and whose failure to perform when proper ly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user. b. a critical component is any component in a life support devic e or system whose failure to perform can be reasonably expect ed to cause the failure of the life support device or to affect its safety or effectiveness. customers represent that they have all necessary expertise in the safety and regulatory ramifi cations of their life support dev ices or systems, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-rel ated requirements concerning the ir products and any use of diodes incorporated products in such safety-critical, life support devices or systems, notwithstanding any devices- or s ystems-related information or support that may be provided by diodes incorporated. further, customers must fully indemnify diodes incorporate d and its representatives against any damages arisi ng out of the use of diodes incorporated pr oducts in such safety-critical, life suppor t devices or systems. copyright ? 2012, diodes incorporated www.diodes.com

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